As a snubber circuit for a neutral point clamping type inverter circuit, an individual snubber circuit type has been employed in general in which a snubber circuit is provided at each of respective switching elements, as disclosed in Japanese Patent Unexamined Publication No. Hei 7-135781 and Japanese Patent Unexamined Publication No. Hei 8-294285.
Japanese Patent Unexamined Publication No. Hei 7-135781 discloses a control method wherein a snubber circuit formed by a resistor, a capacitor and a diode is provided at each of respective switching elements so that an inverter can be stopped without breaking the switching element due to the excessive voltage or the like applied thereto.
Japanese Patent Unexamined Publication No. Hei 8-294285 discloses a technique wherein a snubber circuit formed by a resistor, a capacitor and a diode is provided at each of respective switching elements and each of the snubber circuits is formed as a voltage clamping type snubber circuit to which a half of the power source voltage is applied thereby to reduce the loss of the snubber circuit.
However, in the case of providing a snubber circuit at a neutral point clamping type inverter circuit of a relatively middle or small capacity, if the individual snubber circuit type having a snubber circuit at each of the switching elements is employed, there arises a problem that the number of parts becomes large and the cost of the snubber circuits becomes expensive.
Therefore, an object of the present invention is to provide a three-level neutral point clamping type inverter circuit wherein the snubber circuits are formed by a smaller number of parts